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ARD2
RC2
Airbag Reference Demonstrator using MPC5604P
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ARD2
RC2
Airbag Reference Demonstrator using MPC5604P
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00001 00016 #include "derivative.h" 00017 #include "Compile_Options.h" 00018 #include "CG147.h" 00019 #include "CG147_Diag.h" 00020 #include "HAL.h" 00021 #include "MailScheduler.h" 00022 #include "DSPI.h" 00023 #include "SIU.h" 00024 #include "Utils.h" 00025 /* 00026 ****************************************************************************** 00027 * constants 00028 ****************************************************************************** 00029 */ 00030 /***************Constants defined for SBC POM Built-in Tests******************/ 00032 static const uint8_t cau8SBCTests[] = 00033 { 00034 CG147_TEST_IS_VER_CAP, CG147_TEST_IS_VER_ESR, CG147_TEST_IS_POL_PROT }; 00036 const uint8_t cu8SizeOfSBCTests = N_ELEMENTS(cau8SBCTests); 00038 static const uint8_t cau8SBCTestResults[] = 00039 { 00040 CLEAR, CLEAR, 0x80u }; 00042 static const uint8_t cau8SBCInitialTestAoutRoutes[] = 00043 { 00044 SBC_AOUT_ER1_DIV_10, SBC_AOUT_ER2_DIV_10, SBC_AOUT_ER3_DIV_10, 00045 SBC_AOUT_ER4_DIV_10, SBC_AOUT_ER5_DIV_10, SBC_AOUT_ER6_DIV_10 }; 00049 static const uint16_t cau16AoutHiLimitsPerTest[] = 00050 { 00051 SBC_TEST_VER_CAP_LIMIT_HI, SBC_TEST_VER_ESR_LIMIT_HI, 00052 SBC_TEST_VER_POL_LIMIT_HI }; 00056 static const uint16_t cau16AoutLoLimitsPerTest[] = 00057 { 00058 SBC_TEST_VER_CAP_LIMIT_LO, SBC_TEST_VER_ESR_LIMIT_LO, 00059 SBC_TEST_VER_POL_LIMIT_LO }; 00063 static const uint8_t cau8AoutCheckLimit[] = 00064 { 00065 TRUE, CLEAR, TRUE 00066 }; 00067 /********************Constants defined for SBC FLM Tests***********************/ 00068 const uint8_t cau8SBCInitialTestAoutRoutesIGH[] = 00069 { 00070 SBC_AOUT_IGH1, SBC_AOUT_IGH2, SBC_AOUT_IGH3, SBC_AOUT_IGH4, SBC_AOUT_IGH5, 00071 SBC_AOUT_IGH6, SBC_AOUT_IGH7, SBC_AOUT_IGH8, SBC_AOUT_IGH9, SBC_AOUT_IGH10, 00072 SBC_AOUT_IGH11, SBC_AOUT_IGH12 }; 00073 const uint8_t cau8SBCInitialTestAoutRoutesIGL[] = 00074 { 00075 SBC_AOUT_IGL1, SBC_AOUT_IGL2, SBC_AOUT_IGL3, SBC_AOUT_IGL4, SBC_AOUT_IGL5, 00076 SBC_AOUT_IGL6, SBC_AOUT_IGL7, SBC_AOUT_IGL8, SBC_AOUT_IGL9, SBC_AOUT_IGL10, 00077 SBC_AOUT_IGL11, SBC_AOUT_IGL12 }; 00078 /* ******************Constants defined for SBC AIN Tests***********************/ 00079 static const uint8_t cau8SBCInitialTestAnaHeadSettings[] = 00080 { 00081 /* First tests correspond to ADC tests */ 00082 SBC_AINADC_VAS_SET, SBC_AINADC_REF_BG, SBC_AINADC_REF_BG2, 00083 SBC_AINADC_23REF_BG2, SBC_AINADC_AGND, 00084 /* Next follows a test for the Mux with a reference voltage */ 00085 SBC_AINMUX_NO_SWITCHES, 00086 /* Next we test each Mux channel with all channels connected to GND */ 00087 SBC_AINMUX_NO_SWITCHES, SBC_AINMUX_NO_SWITCHES, SBC_AINMUX_NO_SWITCHES, 00088 SBC_AINMUX_NO_SWITCHES, SBC_AINMUX_NO_SWITCHES, SBC_AINMUX_NO_SWITCHES, 00089 SBC_AINMUX_NO_SWITCHES, SBC_AINMUX_NO_SWITCHES, 00090 /* Now we switch CH1 on and test all channels */ 00091 SBC_AINMUX_AIN1, SBC_AINMUX_AIN1, SBC_AINMUX_AIN1, SBC_AINMUX_AIN1, 00092 SBC_AINMUX_AIN1, SBC_AINMUX_AIN1, SBC_AINMUX_AIN1, SBC_AINMUX_AIN1, 00093 /* Now we switch CH2 on and test all channels */ 00094 SBC_AINMUX_AIN2, SBC_AINMUX_AIN2, SBC_AINMUX_AIN2, SBC_AINMUX_AIN2, 00095 SBC_AINMUX_AIN2, SBC_AINMUX_AIN2, SBC_AINMUX_AIN2, SBC_AINMUX_AIN2, 00096 /* Now we switch CH3 on and test all channels */ 00097 SBC_AINMUX_AIN3, SBC_AINMUX_AIN3, SBC_AINMUX_AIN3, SBC_AINMUX_AIN3, 00098 SBC_AINMUX_AIN3, SBC_AINMUX_AIN3, SBC_AINMUX_AIN3, SBC_AINMUX_AIN3, 00099 /* Now we switch CH4 on and test all channels */ 00100 SBC_AINMUX_AIN4, SBC_AINMUX_AIN4, SBC_AINMUX_AIN4, SBC_AINMUX_AIN4, 00101 SBC_AINMUX_AIN4, SBC_AINMUX_AIN4, SBC_AINMUX_AIN4, SBC_AINMUX_AIN4, 00102 /* Now we switch CH5 on and test all channels */ 00103 SBC_AINMUX_AIN5, SBC_AINMUX_AIN5, SBC_AINMUX_AIN5, SBC_AINMUX_AIN5, 00104 SBC_AINMUX_AIN5, SBC_AINMUX_AIN5, SBC_AINMUX_AIN5, SBC_AINMUX_AIN5, 00105 /* Now we switch CH6 on and test all channels */ 00106 SBC_AINMUX_AIN6, SBC_AINMUX_AIN6, SBC_AINMUX_AIN6, SBC_AINMUX_AIN6, 00107 SBC_AINMUX_AIN6, SBC_AINMUX_AIN6, SBC_AINMUX_AIN6, SBC_AINMUX_AIN6, 00108 /* Now we switch CH7 on and test all channels */ 00109 SBC_AINMUX_AIO1, SBC_AINMUX_AIO1, SBC_AINMUX_AIO1, SBC_AINMUX_AIO1, 00110 SBC_AINMUX_AIO1, SBC_AINMUX_AIO1, SBC_AINMUX_AIO1, SBC_AINMUX_AIO1, 00111 /* Now we switch CH8 on and test all channels */ 00112 SBC_AINMUX_AIO2, SBC_AINMUX_AIO2, SBC_AINMUX_AIO2, SBC_AINMUX_AIO2, 00113 SBC_AINMUX_AIO2, SBC_AINMUX_AIO2, SBC_AINMUX_AIO2, SBC_AINMUX_AIO2, 00114 00115 }; 00116 const uint8_t cu8SizeOfTestAnaHeadSettings 00117 = N_ELEMENTS(cau8SBCInitialTestAnaHeadSettings); 00118 static const uint8_t cau8SBCInitialTestAnaMUXChannel[] = 00119 { 00120 /* First tests correspond to ADC tests - no mux */ 00121 SBC_AINMUX_VOLT, SBC_AINMUX_VOLT, SBC_AINMUX_VOLT, 00122 SBC_AINMUX_VOLT, SBC_AINMUX_VOLT, 00123 /* Next follows a test for the Mux with a reference voltage */ 00124 SBC_AINMUX_VOLT, 00125 /* Next we test each Mux channel with all channels connected to GND */ 00126 SBC_AINMUX_AIN1, SBC_AINMUX_AIN2, SBC_AINMUX_AIN3, SBC_AINMUX_AIN4, 00127 SBC_AINMUX_AIN5, SBC_AINMUX_AIN6, SBC_AINMUX_AIO1, SBC_AINMUX_AIO2, 00128 /* Now we switch CH1 on and test all channels */ 00129 SBC_AINMUX_AIN1, SBC_AINMUX_AIN2, SBC_AINMUX_AIN3, SBC_AINMUX_AIN4, 00130 SBC_AINMUX_AIN5, SBC_AINMUX_AIN6, SBC_AINMUX_AIO1, SBC_AINMUX_AIO2, 00131 /* Now we switch CH2 on and test all channels */ 00132 SBC_AINMUX_AIN1, SBC_AINMUX_AIN2, SBC_AINMUX_AIN3, SBC_AINMUX_AIN4, 00133 SBC_AINMUX_AIN5, SBC_AINMUX_AIN6, SBC_AINMUX_AIO1, SBC_AINMUX_AIO2, 00134 /* Now we switch CH3 on and test all channels */ 00135 SBC_AINMUX_AIN1, SBC_AINMUX_AIN2, SBC_AINMUX_AIN3, SBC_AINMUX_AIN4, 00136 SBC_AINMUX_AIN5, SBC_AINMUX_AIN6, SBC_AINMUX_AIO1, SBC_AINMUX_AIO2, 00137 /* Now we switch CH4 on and test all channels */ 00138 SBC_AINMUX_AIN1, SBC_AINMUX_AIN2, SBC_AINMUX_AIN3, SBC_AINMUX_AIN4, 00139 SBC_AINMUX_AIN5, SBC_AINMUX_AIN6, SBC_AINMUX_AIO1, SBC_AINMUX_AIO2, 00140 /* Now we switch CH5 on and test all channels */ 00141 SBC_AINMUX_AIN1, SBC_AINMUX_AIN2, SBC_AINMUX_AIN3, SBC_AINMUX_AIN4, 00142 SBC_AINMUX_AIN5, SBC_AINMUX_AIN6, SBC_AINMUX_AIO1, SBC_AINMUX_AIO2, 00143 /* Now we switch CH6 on and test all channels */ 00144 SBC_AINMUX_AIN1, SBC_AINMUX_AIN2, SBC_AINMUX_AIN3, SBC_AINMUX_AIN4, 00145 SBC_AINMUX_AIN5, SBC_AINMUX_AIN6, SBC_AINMUX_AIO1, SBC_AINMUX_AIO2, 00146 /* Now we switch CH7 on and test all channels */ 00147 SBC_AINMUX_AIN1, SBC_AINMUX_AIN2, SBC_AINMUX_AIN3, SBC_AINMUX_AIN4, 00148 SBC_AINMUX_AIN5, SBC_AINMUX_AIN6, SBC_AINMUX_AIO1, SBC_AINMUX_AIO2, 00149 /* Now we switch CH8 on and test all channels */ 00150 SBC_AINMUX_AIN1, SBC_AINMUX_AIN2, SBC_AINMUX_AIN3, SBC_AINMUX_AIN4, 00151 SBC_AINMUX_AIN5, SBC_AINMUX_AIN6, SBC_AINMUX_AIO1, SBC_AINMUX_AIO2 00152 }; 00153 static const uint8_t cau8SBCInitialTestAINADCLoLimits[] = 00154 { 00155 /* First tests correspond to ADC tests */ 00156 SBC_TEST_AINADC_VAS_SET_LIMIT_LO, SBC_TEST_AINADC_REF_BG_LIMIT_LO, 00157 SBC_TEST_AINADC_REF_BG2_LIMIT_LO, SBC_TEST_AINADC_REF_23BG2_LIMIT_LO, 00158 SBC_TEST_AINADC_AGND_LIMIT_LO, 00159 /* Next follows a test for the Mux with a reference voltage */ 00160 SBC_TEST_AINMUX_NOSWITCHCLOSED_LIMIT_LO, 00161 /* Next we test each Mux channel with all channels connected to GND */ 00162 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00163 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00164 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00165 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00166 /* Now we switch CH1 on and test all channels */ 00167 SBC_TEST_AINMUX_SWITCHAVST33_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00168 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00169 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00170 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00171 /* Now we switch CH2 on and test all channels */ 00172 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHAVST33_LIMIT_LO, 00173 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00174 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00175 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00176 /* Now we switch CH3 on and test all channels */ 00177 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00178 SBC_TEST_AINMUX_SWITCHAVST33_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00179 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00180 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00181 /* Now we switch CH4 on and test all channels */ 00182 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00183 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHAVST33_LIMIT_LO, 00184 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00185 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00186 /* Now we switch CH5 on and test all channels */ 00187 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00188 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00189 SBC_TEST_AINMUX_SWITCHAVST33_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00190 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00191 /* Now we switch CH6 on and test all channels */ 00192 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00193 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00194 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHAVST33_LIMIT_LO, 00195 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00196 /* Now we switch CH7 on and test all channels */ 00197 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00198 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00199 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00200 SBC_TEST_AINMUX_SWITCHAVST33_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00201 /* Now we switch CH8 on and test all channels */ 00202 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00203 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00204 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00205 SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, SBC_TEST_AINMUX_SWITCHAVST33_LIMIT_LO, 00206 }; 00207 static const uint8_t cau8SBCInitialTestAINADCHiLimits[] = 00208 { 00209 /* First tests correspond to ADC tests */ 00210 SBC_TEST_AINADC_VAS_SET_LIMIT_HI, SBC_TEST_AINADC_REF_BG_LIMIT_HI, 00211 SBC_TEST_AINADC_REF_BG2_LIMIT_HI, SBC_TEST_AINADC_REF_23BG2_LIMIT_HI, 00212 SBC_TEST_AINADC_AGND_LIMIT_HI, 00213 /* Next follows a test for the Mux with a reference voltage */ 00214 SBC_TEST_AINMUX_NOSWITCHCLOSED_LIMIT_HI, 00215 /* Next we test each Mux channel with all channels connected to GND */ 00216 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00217 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00218 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00219 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00220 /* Now we switch CH1 on and test all channels */ 00221 SBC_TEST_AINMUX_SWITCHAVST33_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00222 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00223 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00224 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00225 /* Now we switch CH1 on and test all channels */ 00226 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHAVST33_LIMIT_HI, 00227 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00228 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00229 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00230 /* Now we switch CH1 on and test all channels */ 00231 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00232 SBC_TEST_AINMUX_SWITCHAVST33_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00233 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00234 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00235 /* Now we switch CH1 on and test all channels */ 00236 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00237 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHAVST33_LIMIT_HI, 00238 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00239 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00240 /* Now we switch CH1 on and test all channels */ 00241 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00242 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00243 SBC_TEST_AINMUX_SWITCHAVST33_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00244 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00245 /* Now we switch CH1 on and test all channels */ 00246 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00247 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00248 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHAVST33_LIMIT_HI, 00249 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00250 /* Now we switch CH1 on and test all channels */ 00251 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00252 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00253 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00254 SBC_TEST_AINMUX_SWITCHAVST33_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00255 /* Now we switch CH1 on and test all channels */ 00256 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00257 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00258 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00259 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, SBC_TEST_AINMUX_SWITCHAVST33_LIMIT_HI 00260 }; 00261 static const uint8_t cau8SBCInitialTestAINMUXLoLimits[] = 00262 { 00263 SBC_TEST_AINMUX_NOSWITCHCLOSED_LIMIT_LO, SBC_TEST_AINMUX_SWITCHGND_LIMIT_LO, 00264 SBC_TEST_AINMUX_SWITCHAVST33_LIMIT_LO, }; 00265 static const uint8_t cau8SBCInitialTestAINMUXHiLimits[] = 00266 { 00267 SBC_TEST_AINMUX_SWITCHGND_LIMIT_HI, 00268 SBC_TEST_AINMUX_SWITCHAVST33_LIMIT_HI, }; 00269 /* 00270 ****************************************************************************** 00271 * Globals 00272 ****************************************************************************** 00273 */ 00275 static uint32_t gu32CG147DiagIgnoredResp; 00277 static uint32_t gu32CG147SchedTime; 00278 /* 00279 ****************************************************************************** 00280 * Fns 00281 ****************************************************************************** 00282 */ 00283 /* 00284 ****************************************************************************** 00285 * u32fnSBCPerformInitialTestsPOM 00286 * Functional with Scheduled SPI Tx in 17-bit configuration ONLY 00287 ****************************************************************************** 00288 */ 00289 uint32_t u32fnSBCPerformInitialTestsPOM(const uint8_t u8ERx, 00290 const uint8_t u8TestIndex) 00291 { 00292 /* NOTE: */ 00293 /* This routine uses ADC values that are transferred through the */ 00294 /* DMA into the stack. It is critical that the function is still being */ 00295 /* executed when the DMA is operational. Otherwise, an IVOR3 interrupt */ 00296 /* is possible, best case, or data corruption, worst case. For this */ 00297 /* reason, both the size of the input array (CG147_N_ADC_DATA), and */ 00298 /* the delays here within are not only relevant for the precision of */ 00299 /* the acquired data, but also for the safe execution of this routine. */ 00300 /* If in doubt, don't change them. */ 00301 00302 /* General Status */ 00303 uint32_t u32Status; 00304 /* Used for Raw responses coming from CG147 */ 00305 uint32_t u32RawResponse[2u]; 00306 /* CG147 Response placeholder after being treated */ 00307 uint8_t u8FilteredResult; 00308 /* Scheduler time holder */ 00309 uint32_t u32TimeMarker; 00310 /* Used as time out when waiting for data */ 00311 uint32_t u32TimeOut; 00312 /* ADC results holder */ 00313 uint16_t au16Aout[CG147_N_ADC_DATA + 1u]; 00314 /* Max - min holder */ 00315 uint16_t u16AoutDelta; 00316 00317 /* Init locals */ 00318 u32Status = CLEAR; 00319 u32RawResponse[CLEAR] = CLEAR; 00320 u32RawResponse[1u] = CLEAR; 00321 u8FilteredResult = CLEAR; 00322 u32TimeMarker = CLEAR; 00323 u32TimeOut = CLEAR; 00324 u16AoutDelta = CLEAR; 00325 00326 /* **** POM Built-in Tests (VER CAP, VER ESR, Polarity Protection **********/ 00327 /* Route the correct voltage value to AOUT */ 00328 u32Status = u8fnCG147ScheduleSafeTransfer(CG147_SPI_CONFIG_EXT, 00329 SBC_AOUT_CTRL, 00330 (cau8SBCInitialTestAoutRoutes[u8ERx] 00331 | BIT7), 00332 (uint16_t*)&u32RawResponse, 00333 (uint32_t*)&u32TimeMarker); 00334 /* Wait for the level to take */ 00335 DELAY_MSEC(1u); 00336 00337 /* Store the current Voltage level in Aout. This is our reference point. */ 00338 vfnTransferADCResults(CLEAR, (uint16_t*)&au16Aout, 1u); 00339 00340 /* Schedule the test */ 00341 (void)u8fnCG147ScheduleSafeTest(CG147_SPI_CONFIG_EXT, 00342 cau8SBCTests[u8TestIndex], 00343 (uint32_t*)&u32RawResponse, 00344 (uint16_t*)&(au16Aout) + ((uint16_t)1u), 00345 (uint32_t*)&u32TimeMarker); 00346 00347 /* Wait for scheduler to get the result. Also, wait for DMA to finish */ 00348 /* transferring ADC results into the memory. */ 00349 while ((u32TimeOut <= SBC_TIMEOUT) && 00350 (CLEAR == u32fnSchedIsTxDone(u32TimeMarker))) 00351 { 00352 /* Wait for one click to pass */ 00353 u32TimeOut++; 00354 } 00355 00356 /* Continue if we didn't time-out */ 00357 if(SBC_TIMEOUT != u32TimeOut) 00358 { 00359 /* Analyze the result */ 00360 (void)u8fnCG147ExtractResponse((const uint32_t*)&u32RawResponse[CLEAR], 00361 (uint8_t*)&u8FilteredResult); 00362 00363 /* Test the result */ 00364 if(u8FilteredResult == cau8SBCTestResults[u8TestIndex]) 00365 { 00366 /* Now let's test the ADC reading limits */ 00367 u16AoutDelta = u16fnMaxU16DeltaInArray((const uint16_t*)au16Aout, 00368 N_ELEMENTS(au16Aout)); 00369 if(TRUE == cau8AoutCheckLimit[u8TestIndex]) 00370 { 00371 if(cau16AoutHiLimitsPerTest[u8TestIndex] > u16AoutDelta) 00372 { 00373 /* This means we are ok... */ 00374 if(cau16AoutLoLimitsPerTest[u8TestIndex] < u16AoutDelta) 00375 { 00376 /* Completely ok. We will exit now */ 00377 } 00378 else 00379 { 00380 u32Status = ((BIT0 << u8ERx) | SBC_TEST_LO_LIMIT_FAILED); 00381 } 00382 } 00383 else 00384 { 00385 u32Status = ((BIT0 << u8ERx) | SBC_TEST_HI_LIMIT_FAILED); 00386 } 00387 } 00388 else 00389 { 00390 /* We won't test this limit. */ 00391 } 00392 } 00393 else 00394 { 00395 u32Status = ((BIT0 << u8ERx) | SBC_TEST_UNEXPECTED_SPI_RESULT); 00396 } 00397 } 00398 else 00399 { 00400 u32Status = ((BIT0 << u8ERx) | SBC_TEST_SCHEDULER_FAILED); 00401 } 00402 00403 /* Wait a few msec for the test condition to re-establish into normal */ 00404 /* operation. We need this because of cap charging/discharging */ 00405 DELAY_MSEC(100u); 00406 00407 return (u32Status); 00408 } 00409 /* 00410 ****************************************************************************** 00411 * u32fnSBCPerformInitialTestsFLM 00412 * Functional with Scheduled SPI Tx in 17-bit configuration ONLY 00413 ****************************************************************************** 00414 */ 00415 uint32_t u32fnSBCPerformInitialTestsFLM(const uint16_t cu16SquibMask) 00416 { 00417 /* General Status */ 00418 uint32_t u32Status; 00419 /* Loop counter */ 00420 uint8_t u8Counter; 00421 uint16_t u16ADCReading; 00422 00423 /* Init locals */ 00424 u32Status = CLEAR; 00425 u8Counter = CLEAR; 00426 u16ADCReading = CLEAR; 00427 00428 /* Note that DIS_ALP is expected to be low at this point, which means that */ 00429 /* the application has been running for at least one second. */ 00430 00431 /* ******* FLM, Squib diagnosis (Leakage and resistance measurement) *******/ 00432 for(u8Counter = CLEAR; u8Counter < N_ELEMENTS(cau8SBCInitialTestAoutRoutesIGH); 00433 u8Counter++) 00434 { 00435 /* In case of presence of squib */ 00436 if((BIT0 << u8Counter) & cu16SquibMask) 00437 { 00438 DELAY_MSEC(2u); 00439 /* Route the correct voltage value IGHx to AOUT and Perform high leakage diagnosis */ 00440 u32Status |= u32fnSBCFLMLeakageMeasP1(cau8SBCInitialTestAoutRoutesIGH[u8Counter], 00441 CLEAR); 00442 DELAY_MSEC(2u); 00443 u32Status |= u32fnSBCFLMLeakageMeasP2(CLEAR, u8Counter, 00444 (uint16_t*)&u16ADCReading); 00445 DELAY_MSEC(2u); 00446 /* Route the correct voltage value IGLx to AOUT and Perform high leakage diagnosis */ 00447 u32Status |= u32fnSBCFLMLeakageMeasP1(cau8SBCInitialTestAoutRoutesIGL[u8Counter], 00448 CLEAR); 00449 DELAY_MSEC(2u); 00450 u32Status |= u32fnSBCFLMLeakageMeasP2(CLEAR, u8Counter, 00451 (uint16_t*)&u16ADCReading); 00452 DELAY_MSEC(2u); 00453 /* Route the correct voltage value IGHx to AOUT and Perform low leakage diagnosis */ 00454 u32Status |= u32fnSBCFLMLeakageMeasP1(cau8SBCInitialTestAoutRoutesIGH[u8Counter], TRUE); 00455 DELAY_MSEC(2u); 00456 u32Status |= u32fnSBCFLMLeakageMeasP2(TRUE, u8Counter, 00457 (uint16_t*)&u16ADCReading); 00458 DELAY_MSEC(2u); 00459 /* Route the correct voltage value IGLx to AOUT and Perform low leakage diagnosis */ 00460 u32Status |= u32fnSBCFLMLeakageMeasP1(cau8SBCInitialTestAoutRoutesIGL[u8Counter], TRUE); 00461 DELAY_MSEC(1u); 00462 u32Status |= u32fnSBCFLMLeakageMeasP2(TRUE, u8Counter, 00463 (uint16_t*)&u16ADCReading); 00464 DELAY_MSEC(2u); 00465 /* Perform resistance measurement */ 00466 u32Status |= u32fnSBCFLMResistanceMeasurement(cau8SBCInitialTestAoutRoutesIGH[u8Counter], 00467 cau8SBCInitialTestAoutRoutesIGL[u8Counter], 00468 u8Counter); 00469 } 00470 else 00471 { 00472 /* Nothing */ 00473 } 00474 } 00475 return (u32Status); 00476 } 00477 /* 00478 ****************************************************************************** 00479 * u32fnSBCFLMLeakageMeasurement 00480 * Functional with Scheduled SPI Tx in 17-bit configuration ONLY 00481 ****************************************************************************** 00482 */ 00483 uint32_t u32fnSBCFLMLeakageMeasP1(uint8_t u8IgnitionPin, uint8_t u8LowLeakage) 00484 { 00485 /* General Status */ 00486 uint32_t u32Status; 00487 /* Local variable for argument */ 00488 uint8_t u8Argu; 00489 00490 /* Init variables */ 00491 u32Status = CLEAR; 00492 u8Argu = CLEAR; 00493 00494 if(CLEAR != u8LowLeakage) 00495 { 00496 /* Activation of low leakage measurement */ 00497 u32Status = u8fnCG147ScheduleSafeTransfer(CG147_SPI_CONFIG_EXT, 00498 SBC_LOWLEAK, ((uint8_t)0x01u), 00499 (uint16_t*)&gu32CG147DiagIgnoredResp, 00500 (uint32_t*)&gu32CG147SchedTime); 00501 00502 /* Amplification v5 activated to increase accuracy with low level implied */ 00503 u8Argu = (uint8_t)(BIT7 | BIT6 | u8IgnitionPin); 00504 } 00505 else 00506 { 00507 u8Argu = (uint8_t)(BIT7 | u8IgnitionPin); 00508 } 00509 00510 /* IGH and IGL on AOUT for ADC conversion */ 00511 u32Status |= u8fnCG147ScheduleSafeTransfer(CG147_SPI_CONFIG_EXT, 00512 SBC_AOUT_CTRL, 00513 u8Argu, 00514 (uint16_t*)&gu32CG147DiagIgnoredResp, 00515 (uint32_t*)&gu32CG147SchedTime); 00516 00517 /* Wait for the level to take, but do it somewhere else */ 00518 return(u32Status); 00519 } 00520 /* 00521 ****************************************************************************** 00522 * u32fnSBCFLMLeakageMeasP2 00523 * Functional with Scheduled SPI Tx in 17-bit configuration ONLY 00524 ****************************************************************************** 00525 */ 00526 uint32_t u32fnSBCFLMLeakageMeasP2(uint8_t u8LowLeakage, uint8_t u8Counter, 00527 uint16_t* pu16Aout) 00528 { 00529 /* Local variable for flag error activation */ 00530 uint32_t u32FlagError; 00531 /* Local variable for high and low limits */ 00532 uint16_t u16HighLimit; 00533 uint16_t u16LowLimit; 00534 uint32_t u32Status; 00535 00536 /* Init variables */ 00537 u32Status = CLEAR; 00538 u16LowLimit = CLEAR; 00539 u16HighLimit = CLEAR; 00540 u32FlagError = CLEAR; 00541 00542 /* Store the current Voltage level in Aout */ 00543 vfnTransferADCResults(CLEAR, pu16Aout, TRUE); 00544 00545 /* Figure out what the limits should be based on u8LowLeakage */ 00546 if(CLEAR != u8LowLeakage) 00547 { 00548 u16HighLimit = SBC_TEST_FLM_LOWLEAK_LIMIT_HI; 00549 u16LowLimit = SBC_TEST_FLM_LOWLEAK_LIMIT_LO; 00550 u32FlagError = SBC_TEST_FLM_LOWLEAK_FAILED; 00551 } 00552 else 00553 { 00554 /* No Low leakage activation */ 00555 u16HighLimit = SBC_TEST_FLM_LEAK_LIMIT_HI; 00556 u16LowLimit = SBC_TEST_FLM_LEAK_LIMIT_LO; 00557 u32FlagError = SBC_TEST_FLM_LEAK_FAILED; 00558 } 00559 00560 /* De-activation of low leakage measurement */ 00561 u32Status = u8fnCG147ScheduleSafeTransfer(CG147_SPI_CONFIG_EXT, 00562 SBC_LOWLEAK, CLEAR, 00563 (uint16_t*)&gu32CG147DiagIgnoredResp, 00564 (uint32_t*)&gu32CG147SchedTime); 00565 00566 /* Diagnosis on ADC value */ 00567 if(CLEAR == u32Status) 00568 { 00569 if(u16HighLimit > *pu16Aout) 00570 { 00571 /* This means we are ok... */ 00572 if(u16LowLimit < *pu16Aout) 00573 { 00574 /* Completely ok, meaning no leakage detection. We will exit now */ 00575 } 00576 else 00577 { 00578 u32Status = ((BIT0 << u8Counter) | u32FlagError); 00579 } 00580 } 00581 else 00582 { 00583 u32Status = ((BIT0 << u8Counter) | u32FlagError); 00584 } 00585 } 00586 else 00587 { 00588 u32Status = ((BIT0 << u8Counter) | SBC_TEST_SCHEDULER_FAILED); 00589 } 00590 return (u32Status); 00591 } 00592 /* 00593 ****************************************************************************** 00594 * u32fnSBCFLMResistanceMeasurement 00595 * Functional with Scheduled SPI Tx in 17-bit configuration ONLY 00596 ****************************************************************************** 00597 */ 00598 uint32_t u32fnSBCFLMResistanceMeasurement(const uint8_t u8IgnitionPinHigh, 00599 const uint8_t u8IgnitionPinLow, 00600 const uint8_t u8Counter) 00601 { 00602 /* NOTE: */ 00603 /* This routine uses ADC values that are transferred through the */ 00604 /* DMA into the stack. It is critical that the function is still being */ 00605 /* executed when the DMA is operational. Otherwise, an IVOR3 interrupt */ 00606 /* is possible, best case, or data corruption, worst case. For this */ 00607 /* reason, both the size of the input array (CG147_N_ADC_DATA), and */ 00608 /* the delays here within are not only relevant for the precision of */ 00609 /* the acquired data, but also for the safe execution of this routine. */ 00610 /* If in doubt, don't change them. */ 00611 00612 uint32_t u32Status; 00613 uint16_t u16SQREF; 00614 uint16_t u16IGH; 00615 uint16_t u16IGL; 00616 uint16_t u16Resistance; 00617 /* Used as time out when waiting for data */ 00618 uint32_t u32TimeOut; 00619 00620 /* Init variables */ 00621 u32Status = CLEAR; 00622 u32TimeOut = CLEAR; 00623 00624 /* ***************** Set current level 40mA or 57mA **********************/ 00625 u32Status = u8fnCG147ScheduleSafeTransfer(CG147_SPI_CONFIG_EXT, 00626 SBC_PROG_FLM_CONF, 0x01 , 00627 (uint16_t*)&gu32CG147DiagIgnoredResp, 00628 (uint32_t*)&gu32CG147SchedTime); 00629 00630 /* First, measuring the exact level of the test current by mean of SQREF **/ 00631 u32Status |= u8fnCG147ScheduleSafeTransfer(CG147_SPI_CONFIG_EXT, 00632 SBC_FLM_TEST_SRC, 00633 0x0D, 00634 (uint16_t*)&gu32CG147DiagIgnoredResp, 00635 (uint32_t*)&gu32CG147SchedTime); 00636 00637 u32Status |= u8fnCG147ScheduleSafeTransfer(CG147_SPI_CONFIG_EXT, 00638 SBC_AOUT_CTRL, 00639 (BIT7 | BIT6 | SBC_AOUT_SQREF), 00640 (uint16_t*)&gu32CG147DiagIgnoredResp, 00641 (uint32_t*)&gu32CG147SchedTime); 00642 /* Wait for the level to take */ 00643 DELAY_MSEC(1u); 00644 00645 /* Store the current Voltage level in Aout */ 00646 vfnTransferADCResults(CLEAR, (uint16_t*)&u16SQREF, TRUE); 00647 00648 u32Status |= u8fnCG147ScheduleSafeTransfer(CG147_SPI_CONFIG_EXT, 00649 SBC_FLM_TEST_SRC, 00650 CLEAR, 00651 (uint16_t*)&gu32CG147DiagIgnoredResp, 00652 (uint32_t*)&gu32CG147SchedTime); 00653 /* Only continue if the pin is low */ 00654 if(CLEAR == u8fnReadPin(PIN_DIS_ALP)) 00655 { 00656 /* ******** Second, IGH and IGL on AOUT with ADC conversions *************/ 00657 u32Status |= u8fnCG147ScheduleSafeTransfer(CG147_SPI_CONFIG_EXT, 00658 SBC_FLM_TEST_SINK, 00659 (u8Counter + 1u), 00660 (uint16_t*)&gu32CG147DiagIgnoredResp, 00661 (uint32_t*)&gu32CG147SchedTime); 00662 00663 u32Status |= u8fnCG147ScheduleSafeTransfer(CG147_SPI_CONFIG_EXT, 00664 SBC_FLM_TEST_SRC, 00665 (u8Counter + 1u), 00666 (uint16_t*)&gu32CG147DiagIgnoredResp, 00667 (uint32_t*)&gu32CG147SchedTime); 00668 00669 u32Status |= u8fnCG147ScheduleSafeTransfer(CG147_SPI_CONFIG_EXT, 00670 SBC_AOUT_CTRL, 00671 (BIT7 | BIT6 | u8IgnitionPinHigh), 00672 (uint16_t*)&gu32CG147DiagIgnoredResp, 00673 (uint32_t*)&gu32CG147SchedTime); 00674 /* Wait for the level to take */ 00675 DELAY_MSEC(1u); 00676 00677 /* Store the current Voltage level in Aout */ 00678 vfnTransferADCResults(CLEAR, (uint16_t*)&u16IGH, 1u); 00679 00680 u32Status |= u8fnCG147ScheduleSafeTransfer(CG147_SPI_CONFIG_EXT, 00681 SBC_AOUT_CTRL, 00682 (BIT7 | BIT6 | u8IgnitionPinLow), 00683 (uint16_t*)&gu32CG147DiagIgnoredResp, 00684 (uint32_t*)&gu32CG147SchedTime); 00685 /* Wait for the level to take */ 00686 DELAY_MSEC(5u); 00687 00688 /* Store the current Voltage level in Aout */ 00689 vfnTransferADCResults(CLEAR, (uint16_t*)&u16IGL, 1u); 00690 00691 u32Status |= u8fnCG147ScheduleSafeTransfer(CG147_SPI_CONFIG_EXT, 00692 SBC_FLM_TEST_SINK, 00693 CLEAR, 00694 (uint16_t*)&gu32CG147DiagIgnoredResp, 00695 (uint32_t*)&gu32CG147SchedTime); 00696 00697 u32Status |= u8fnCG147ScheduleSafeTransfer(CG147_SPI_CONFIG_EXT, 00698 SBC_FLM_TEST_SRC, 00699 CLEAR, 00700 (uint16_t*)&gu32CG147DiagIgnoredResp, 00701 (uint32_t*)&gu32CG147SchedTime); 00702 00703 /*************************************Third, Diagnosis***********************************/ 00704 00705 /* 68u for SQREF resistance = 6.8Ohm */ 00706 u16Resistance = (uint16_t)((SBC_SQREF_RESISTANCE * (u16IGH - u16IGL) / u16SQREF)); 00707 00708 /* Wait for scheduler to get the result. Also, wait for DMA to finish */ 00709 /* transferring ADC results into the memory. */ 00710 while ((u32TimeOut <= SBC_TIMEOUT) && 00711 (CLEAR == u32fnSchedIsTxDone(gu32CG147SchedTime))) 00712 { 00713 /* Wait for one click to pass */ 00714 u32TimeOut++; 00715 } 00716 /* Continue if we didn't time-out */ 00717 if((SBC_TIMEOUT != u32TimeOut) & (CLEAR == u32Status)) 00718 { 00719 if(SBC_SQUIB_RESISTANCE_LIMIT_HI > u16Resistance) 00720 { 00721 /* This means we are ok... */ 00722 if(SBC_SQUIB_RESISTANCE_LIMIT_LO < u16Resistance) 00723 { 00724 /* Resistance measured is correct. We will exit now */ 00725 } 00726 else 00727 { 00728 u32Status = ((BIT0 << u8Counter) | SBC_TEST_FLM_RESISTANCE_FAILED); 00729 } 00730 } 00731 else 00732 { 00733 u32Status = ((BIT0 << u8Counter) | SBC_TEST_FLM_RESISTANCE_FAILED); 00734 } 00735 } 00736 else 00737 { 00738 u32Status = ((BIT0 << u8Counter) | SBC_TEST_SCHEDULER_FAILED); 00739 } 00740 } 00741 else 00742 { 00743 u32Status = SBC_TEST_DIS_ALP_FAILED; 00744 } 00745 return (u32Status); 00746 } 00747 /* 00748 ****************************************************************************** 00749 * u32fnSBCTestMuxAndADC 00750 * Functional with Scheduled SPI Tx in 17-bit configuration ONLY 00751 ****************************************************************************** 00752 */ 00753 uint32_t u32fnSBCTestMuxAndADC(uint8_t u8TestIndex) 00754 { 00755 /* General Status */ 00756 uint32_t u32Status; 00757 /* Used as time out when waiting for data */ 00758 uint32_t u32TimeOut; 00759 uint32_t u32RawADCResponse; 00760 uint8_t u8SBCADCResult; 00761 00762 /* Init locals */ 00763 u32Status = CLEAR; 00764 u32TimeOut = CLEAR; 00765 u32RawADCResponse = CLEAR; 00766 u8SBCADCResult = CLEAR; 00767 00768 00769 /* ************************* SBC_TEST_ANA_HEAD ****************************/ 00770 u32Status |= u8fnCG147ScheduleSafeTransfer(CG147_SPI_CONFIG_EXT, 00771 SBC_TEST_ANA_HEAD, 00772 cau8SBCInitialTestAnaHeadSettings[u8TestIndex], 00773 (uint16_t*)&gu32CG147DiagIgnoredResp, 00774 (uint32_t*)&gu32CG147SchedTime); 00775 00776 /* ****************** SBC_START_ADC *************************/ 00777 u32Status |= u8fnCG147ScheduleSafeTransfer(CG147_SPI_CONFIG_EXT, 00778 SBC_START_ADC, 00779 cau8SBCInitialTestAnaMUXChannel[u8TestIndex], 00780 (uint16_t*)&gu32CG147DiagIgnoredResp, 00781 (uint32_t*)&gu32CG147SchedTime); 00782 00783 /* Wait for the ADC to be ready */ 00784 DELAY_MSEC(1u); 00785 00786 /* Read ADC */ 00787 u32Status |= u8fnCG147ScheduleSafeTransfer(CG147_SPI_CONFIG_EXT, 00788 SBC_READ_ADC, 00789 0x01, 00790 (uint16_t*)&u32RawADCResponse, 00791 (uint32_t*)&gu32CG147SchedTime); 00792 00793 /* Wait for scheduler to get the result */ 00794 while ((u32TimeOut <= SBC_TIMEOUT) && 00795 (CLEAR == u32fnSchedIsTxDone(gu32CG147SchedTime))) 00796 { 00797 /* Wait for one click to pass */ 00798 u32TimeOut++; 00799 } 00800 /* Continue if we didn't time-out */ 00801 if((SBC_TIMEOUT != u32TimeOut) & (CLEAR == u32Status)) 00802 { 00803 /* Extract ADC result */ 00804 u32Status = u8fnCG147ExtractResponse((const uint32_t*)&u32RawADCResponse, 00805 (uint8_t*)&u8SBCADCResult); 00806 if(((CG147_END_OF_PROGRAMMING_FLAG >> BITS_IN_BYTE) == u32Status) || 00807 (CLEAR == u32Status)) 00808 { 00809 if(cau8SBCInitialTestAINADCHiLimits[u8TestIndex] >= u8SBCADCResult) 00810 { 00811 /* This means we are ok... */ 00812 if(cau8SBCInitialTestAINADCLoLimits[u8TestIndex] <= u8SBCADCResult) 00813 { 00814 /* Completely ok, meaning no leakage detection. We will exit now */ 00815 } 00816 else 00817 { 00818 u32Status = (SBC_TEST_SBC_ADC_FAILED); 00819 } 00820 } 00821 else 00822 { 00823 u32Status = (SBC_TEST_SBC_ADC_FAILED); 00824 } 00825 } 00826 else 00827 { 00828 u32Status = (SBC_TEST_SCHEDULER_FAILED); 00829 } 00830 } 00831 else 00832 { 00833 u32Status = (SBC_TEST_SCHEDULER_FAILED); 00834 } 00835 return (u32Status); 00836 } 00837 /* 00838 ****************************************************************************** 00839 * 00840 * End of file. 00841 * 00842 ****************************************************************************** 00843 */
1.7.5.1 
